The present disclosure relates to a nonvolatile semiconductor storage device including resistive memory cells each of which includes a variable resistance element and a cell transistor for selecting the variable resistance element, which are connected together in series. More particularly, the present disclosure relates to a technique of stabilizing resistance values in a low resistance state and a high resistance state of the variable resistance element irrespective of variations in the cell transistor and thereby improving read characteristics and reliability characteristics of the nonvolatile semiconductor storage device.
There has in recent years been an increasing demand for electronic apparatuses, particularly mobile telephones (smartphones), portable music players, digital cameras, tablet terminals, etc., leading to an increasing demand for nonvolatile semiconductor storage devices. Various technologies for further improving capacity, size, write speed, read speed, and low power consumption operation are currently under development.
Flash memory dominates the nonvolatile memory market today. However, the write time is topping out at as low as the microsecond or millisecond scale. This is a factor that inhibits improvement in performance of set apparatuses including the nonvolatile memory device.
Various alternative nonvolatile memory technologies that can write at higher speed and lower power consumption than those of flash memory have in recent years been developed. One of such nonvolatile memory devices is, for example, resistive random access memory (ReRAM), which employs a variable resistance element as a memory element. Resistive random access memory can have a nanosecond-scale write time, i.e., can perform high-speed write. In addition, a voltage used to write in resistive random access memory is about 1.6 V compared to 10 V or more in flash memory, which allows the nonvolatile memory to operate with lower power consumption.
Japanese Unexamined Patent Publication No. 2004-234707 describes a memory array configuration of resistive random access memory. A memory cell in resistive random access memory includes a series connection of a variable resistance element and a cell transistor. The variable resistance element stores data (“0” or “1”) according to whether the variable resistance element is set to a low resistance value or a high resistance value, where the resistance value ranges from 1 kΩ to 1 MΩ, for example. When the resistance value of the variable resistance element is low, the memory cell current is large. When the resistance value of the variable resistance element is high, the memory cell current is small. Therefore, by detecting the difference in memory cell current using a sense amplifier circuit during read operation, data stored in a memory cell is read out.
Japanese Unexamined Patent Publication No. 2008-052781 describes a programming circuit configuration of resistive random access memory. The variable resistance element is reversibly switched between the low and high resistance states, depending on the polarity of a voltage applied to the opposite ends of the variable resistance element.
However, the above conventional nonvolatile resistive random access memory has the following problem. Specifically, the resistance values in the high and low resistance states depend on a voltage applied to the variable resistance element during program operation or erase operation, and such a voltage is largely affected by the threshold voltage of the cell transistor. Therefore, the resistance values in the high and low resistance states vary depending on manufacturing variations in the threshold voltage of the cell transistor.
The above problem will be described with reference to FIGS. 1, 2, 3, and 4.
FIG. 1 shows a resistive memory cell including a series connection of a variable resistance element RR and a cell transistor TC.
FIG. 2 shows values of voltages applied to terminals of a resistive memory cell including a series connection of a variable resistance element RR and a cell transistor TC, which is included in a conventional nonvolatile semiconductor storage device, during program operation, erase operation, and read operation.
In the memory cell, the gate of the cell transistor is connected to a word line WL, a terminal closer to the variable resistance element is connected to a bit line BL, and a terminal closer to the cell transistor is connected to a source line SL.
During program operation of the memory cell, a program word line voltage Vg_reset (e.g., 2.4 V) is applied to the word line WL, so that the memory cell is in the conducting state, and a program bit line voltage Vreset (e.g., 2.4 V) is applied to the bit line BL and a ground voltage VSS is applied to the source line SL, and therefore, a voltage VR applied to the variable resistance element RR causes the memory cell to be in the high resistance state.
During erase operation, an erase word line voltage Vg_set (e.g., 2.4 V) is applied to the word line WL, so that the memory cell is in the conducting state, and the ground voltage VSS is applied to the bit line BL and an erase voltage Vset (e.g., 2.4 V) is applied to the source line SL, so that the voltage VR applied to the variable resistance element RR causes the memory cell to be in the low resistance state.
During read operation, a read word line voltage Vg_read (e.g., 1.8 V) is applied to the word line WL, so that the cell transistor is in the conducting state. Thereafter, a read bit line voltage Vread (e.g., 0.4 V) is applied to the bit line BL and the ground voltage VSS is applied to the source line SL, so that a current flows through the memory cell. The current is small when the variable resistance element RR is in the high resistance state and large when the variable resistance element RR is in the low resistance state. Based on this, the data state is determined.
FIG. 3 shows current-voltage characteristics of the resistive memory cell during program operation or erase operation. The voltage (VR) indicates a voltage applied to the variable resistance element RR during the program operation or erase operation, and the current indicates a value of a current flowing at that time.
Here, during erase operation in which the variable resistance element RR is caused to be in the low resistance state, the voltage VR applied to the variable resistance element RR varies depending on the threshold voltage of the cell transistor TC, and is lower than the erase source line voltage Vset. Therefore, if the threshold voltage of the cell transistor TC is low, the voltage VR applied is relatively high, and the resistance value after erase operation becomes low (current-voltage characteristics 40). If the threshold voltage of the cell transistor TC is high, the voltage VR applied is relatively low, and the resistance value after erase operation becomes high (current-voltage characteristics 41).
During program operation in which the variable resistance element RR is caused to be in the high resistance state, if the threshold voltage of the cell transistor TC is low, the resistance value after program operation becomes high. If the threshold voltage is high, the resistance value after program operation becomes low. Note that, as compared to erase operation, the reduction in the voltage VR applied to the variable resistance element RR with respect to the program bit line voltage Vreset is low and therefore has a relatively small influence.
FIG. 4 shows a distribution of a current flowing through the memory cell during read operation after the above program operation or erase operation in a nonvolatile semiconductor storage device including a plurality of resistive memory cells. A distribution in a region having high cell currents during read operation is a bit current distribution after erase operation, and a distribution in a region having low cell currents during read operation is a bit current distribution after program operation. During read operation, data is determined by comparison with a predetermined read reference current (Iref).
When the threshold voltage of the cell transistor TC is low due to the influence of the threshold voltage of the cell transistor TC on the resistance value after write operation, the resistance value after erase operation becomes low, so that the bit current distribution (bit current distribution 50) is located in a region where the current is high, and the resistance value after program operation becomes high, so that the bit current distribution (bit current distribution 50) is located in a region where the current is low.
On the other hand, if the threshold voltage of the cell transistor TC is high, the resistance value after erase operation becomes high, so that the bit current distribution (bit current distribution 51) is located in a region where the current is lower than in the bit current distribution 50, and the resistance value after program operation becomes low, so that the bit current distribution (bit current distribution 51) is located in a region where the current is higher than in the bit current distribution 50.
Thus, the influence of the threshold voltage of the cell transistor TC on the bit current distribution after write operation affects reliability characteristics, such as read operation characteristics, repetitive write characteristics, etc.
For example, the bit current distribution 50 can have a larger current difference 52 than a current difference 53 between the bit current distribution after write operation in the bit current distribution 51 and the reference current (Iref). Therefore, to improve read operation characteristics, it is necessary to cause the voltage VR applied to the variable resistance element RR during write operation to be higher than or equal to a predetermined voltage. However, this does not mean that any high voltage is effective. If a predetermined voltage or more is applied, repetitive write characteristics may be adversely affected. For example, the variable resistance element RR may not be switched from the high resistance state to the low resistance state, or from the low resistance state to the high resistance state, so that write operation cannot be performed. Therefore, the voltage VR may be limited to a predetermined voltage or less.
Thus, to allow a nonvolatile semiconductor storage device including resistive memory cells to have write operation that simultaneously has good read operation characteristics and repetitive write characteristics, it is necessary to optimize the voltage applied to the variable resistance element RR during write operation.
However, in conventional nonvolatile semiconductor storage devices, a predetermined voltage is applied during write operation, and therefore, if there are manufacturing variations in threshold voltage of the cell transistor TC, the voltage VR applied to the variable resistance element RR during write operation varies, and therefore, it is difficult to apply an optimal voltage to the variable resistance element RR.